1. Field of the Invention
The present invention relates to a flash memory system, and more particularly, to a method of writing and reading data and parity codes in a flash memory system.
2. Description of the Related Art
In general, a flash memory device is a kind of nonvolatile electrically erasable and programmable read only memory (“EEPROM”), which does not have to be refreshed.
The flash memory device can be categorized as either NOR or NAND type. While a NOR flash memory device accepts a small amount of data at high speed, a NAND flash memory device accepts a large amount of data.
Programming and erasing of a typical NAND flash memory entail controlling of the threshold voltage of a memory cell by injecting and emitting electrons into and from a floating gate.
This NAND flash memory comprises a register, which is typically referred to as a “page buffer,” to write a large amount of data in a short amount of time.
Data that has been externally input is written in a memory cell array via the page buffer, and data that has been read from the memory cell array is externally output via the page buffer. Accordingly, data is typically written and read in and from the flash memory in units of the size of the page buffer.
Meanwhile, in a system including a NAND flash memory device, data is written along with a parity code for the data in order to check and/or correct data errors.
A controller generates a parity code for a certain amount of data and writes the data along with the parity code in the flash memory device. Thereafter, the controller reads the parity code from the flash memory device and checks whether or not the data has errors.
With a recent increase in the size of the page buffer of the flash memory, a unit for processing parity codes has also increased. Normally, a parity code is generated for data having a size equal to the size of the page buffer.
That is, the unit of processing parity codes corresponds to data having a size equal to the size of the page buffer. Thus, with increasing the size of the page buffer, hardware for generating parity codes becomes more complicated or overall processing time increases.